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20 lines
474 B
Systemverilog
20 lines
474 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int array[5];
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bit [1:0] rd_addr;
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wire int rd_value = read_array[rd_addr]; //<--- Warning
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ok ok();
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endmodule
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module ok;
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int array[5];
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bit [1:0] rd_addr;
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wire int rd_value = read_array[{1'b0, rd_addr}]; //<--- Fixed
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endmodule;
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