verilator/test_regress/t/t_c_this.v

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
always @(posedge clk) begin
$c("const CData xthis = this->clk;");
$c("const CData thisx = xthis;");
$c("const CData xthisx = thisx;");
$c("this->clk = xthisx;");
end
endmodule