mirror of
https://github.com/verilator/verilator.git
synced 2025-01-10 00:27:35 +00:00
4 lines
270 B
Plaintext
4 lines
270 B
Plaintext
|
%Warning-WIDTH: t/t_lint_restore_bad.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
|
||
|
|
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|
||
|
|
%Error: Exiting due to
|