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88 lines
1.8 KiB
Coq
88 lines
1.8 KiB
Coq
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// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [31:0] a;
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reg [31:0] b;
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wire [1:0] bf; buf BF0 (bf[0], a[0]),
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BF1 (bf[1], a[1]);
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// verilator lint_off IMPLICIT
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not NT0 (nt0, a[0]);
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and AN0 (an0, a[0], b[0]);
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nand ND0 (nd0, a[0], b[0], b[1]);
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or OR0 (or0, a[0], b[0]);
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nor NR0 (nr0, a[0], b[0], b[2]);
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xor (xo0, a[0], b[0]);
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xnor (xn0, a[0], b[0], b[2]);
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// verilator lint_on IMPLICIT
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`ifdef verilator
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specify
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specparam CDS_LIBNAME = "foobar";
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(nt0 *> nt0) = (0, 0);
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endspecify
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specify
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// delay parameters
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specparam
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a$A1$Y = 1.0,
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b$A0$Z = 1.0;
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// path delays
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(A1 *> Q) = (a$A1$Y, a$A1$Y);
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(A0 *> Q) = (b$A0$Y, a$A0$Z);
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endspecify
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`endif
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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a <= 32'h18f6b034;
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b <= 32'h834bf892;
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end
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if (cyc==2) begin
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a <= 32'h529ab56f;
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b <= 32'h7835a237;
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if (bf[0] !== 1'b0) $stop;
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if (bf[1] !== 1'b0) $stop;
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if (nt0 !== 1'b1) $stop;
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if (an0 !== 1'b0) $stop;
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if (nd0 !== 1'b1) $stop;
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if (or0 !== 1'b0) $stop;
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if (nr0 !== 1'b1) $stop;
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if (xo0 !== 1'b0) $stop;
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if (xn0 !== 1'b1) $stop;
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end
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if (cyc==3) begin
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if (bf[0] !== 1'b1) $stop;
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if (bf[1] !== 1'b1) $stop;
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if (nt0 !== 1'b0) $stop;
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if (an0 !== 1'b1) $stop;
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if (nd0 !== 1'b0) $stop;
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if (or0 !== 1'b1) $stop;
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if (nr0 !== 1'b0) $stop;
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if (xo0 !== 1'b0) $stop;
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if (xn0 !== 1'b0) $stop;
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end
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if (cyc==4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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