2006-08-26 11:35:28 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 15:24:24 +00:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2006-08-26 11:35:28 +00:00
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module t;
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initial begin
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if (add(3'd1) != 0) $stop; // Too few args
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2019-06-13 02:22:36 +00:00
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if (add(3'd1, 3'd2, 3'd3) != 0) $stop; // Too many args
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2006-08-26 11:35:28 +00:00
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x; // Too few args
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if (hasout(3'd1) != 0) $stop; // outputs
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2013-08-18 00:34:49 +00:00
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//
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f(.j(1), .no_such(2)); // Name mismatch
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f(.dup(1), .dup(3)); // Duplicate
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f(1,2,3); // Too many
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2006-08-26 11:35:28 +00:00
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end
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function [2:0] add;
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input [2:0] from1;
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input [2:0] from2;
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begin
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2019-06-13 02:22:36 +00:00
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add = from1 + from2;
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2006-08-26 11:35:28 +00:00
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end
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endfunction
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task x;
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output y;
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begin end
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endtask
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function hasout;
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output [2:0] illegal_output;
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hasout = 0;
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endfunction
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2023-01-05 22:42:05 +00:00
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function automatic int f( int j = 1, int dup = 0 );
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2013-08-18 00:34:49 +00:00
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return (j<<16) | dup;
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endfunction
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2006-08-26 11:35:28 +00:00
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endmodule
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