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40 lines
825 B
Systemverilog
40 lines
825 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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endclass : Cls
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typedef struct {
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Cls obj;
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int number;
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} str_t;
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module t (/*AUTOARG*/);
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function automatic str_t func_null();
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return '{null, 42};
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endfunction
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function automatic str_t func_obj();
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Cls c;
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c = new;
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return '{c, 43};
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endfunction
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initial begin
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str_t result;
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result = func_null();
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if (result.obj != null) $stop;
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if (result.number != 42) $stop;
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result = func_obj();
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if (result.obj == null) $stop;
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if (result.number != 43) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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