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37 lines
660 B
Systemverilog
37 lines
660 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int rf;
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int state;
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constraint c { rf == state; }
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endclass
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module t (/*AUTOARG*/);
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Packet p;
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int v;
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initial begin
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p = new;
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p.state = 123;
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v = p.randomize();
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if (v != 1) $stop;
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if (p.rf != 123) $stop;
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p.state = 234;
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v = p.randomize();
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if (v != 1) $stop;
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if (p.rf != 234) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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