2006-08-26 11:35:28 +00:00
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#!/usr/bin/perl
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2008-09-23 14:02:31 +00:00
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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2006-08-26 11:35:28 +00:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2009-05-04 21:07:57 +00:00
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# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
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2006-08-26 11:35:28 +00:00
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# redistribute it and/or modify it under the terms of either the GNU
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2009-05-04 21:07:57 +00:00
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2006-08-26 11:35:28 +00:00
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2018-05-08 00:42:28 +00:00
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scenarios(simulator => 1);
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2007-12-13 13:54:04 +00:00
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top_filename("t/t_trace_ena.v");
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2018-05-07 02:39:18 +00:00
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compile(
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2018-01-30 00:07:49 +00:00
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verilator_flags2 => ['-trace'],
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);
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2006-08-26 11:35:28 +00:00
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2018-05-07 02:39:18 +00:00
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execute(
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check_finished => 1,
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2018-01-30 00:07:49 +00:00
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);
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2006-08-26 11:35:28 +00:00
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2018-05-08 23:39:32 +00:00
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if ($Self->{vlt_all}) {
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2008-11-25 02:38:45 +00:00
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file_grep ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/c_trace_on\"/x);
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file_grep_not ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/_trace_off\"/x);
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file_grep ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
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2014-11-08 19:15:10 +00:00
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file_grep_not ("$Self->{obj_dir}/simx.vcd", qr/inside_sub/x);
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2018-01-30 00:07:49 +00:00
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2019-05-02 23:02:40 +00:00
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vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
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2006-08-26 11:35:28 +00:00
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}
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ok(1);
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1;
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