2012-07-29 14:16:20 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module x;
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typedef struct {
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2018-10-27 14:03:28 +00:00
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int a;
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2012-07-29 14:16:20 +00:00
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} notpacked_t;
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typedef struct packed {
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2013-10-29 00:41:05 +00:00
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notpacked_t b;
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2012-07-29 14:16:20 +00:00
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} ispacked_t;
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2013-10-29 00:41:05 +00:00
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ispacked_t p;
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initial begin
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p.b = 1;
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if (p.b != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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2012-07-29 14:16:20 +00:00
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endmodule
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