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29 lines
502 B
Systemverilog
29 lines
502 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit p = 0, q = 0;
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initial begin
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t1(p);
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t2(q);
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if (p != 1) $stop;
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if (q != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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task t1(inout p);
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fork
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p = 1;
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join_none
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endtask
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task t2(output q);
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q <= 1;
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endtask
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endmodule
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