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23 lines
691 B
Systemverilog
23 lines
691 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2023 by Don Williamson and Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module top;
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string scope;
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initial begin
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scope = $sformatf("%m");
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$write("[%0t] In %s\n", $time, scope);
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`ifdef MAIN_TOP_NAME_EMPTY
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if (scope != "top") $stop;
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`else
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if (scope != "ALTOP.top") $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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