verilator/test_regress/t/t_dfg_3872.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0

module top(
  input  wire [1:0] i,
  output wire [3:0] o
);
  assign o = 4'd2 ** i;
endmodule
Allow mismatched widths in operands of shifts in DFG Fixes #3872. Testing this is a bit tricky, as the front-end fixes up the operand widths in shifts to match, and we need V3Const to introduce a mismatched one by reducing `4'd2 ** x` (with x being 2 2-bit wide signal) to `4'd1 << x`, but t_dfg_peephole runs with V3Const disabled exactly because it makes it hard to write tests. Rather than fixing this one case in V3Const (which we should do systematically at some point), I fixed DFG to accept these just in case V3Const generates more of them. The assertions were there only because of paranoia (as I thought these were not possible inputs), the code otherwise works. 2023-01-22 10:43:16 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
			`// This file ONLY is placed under the Creative Commons Public Domain, for`
			`// any use, without warranty, 2023 by Geza Lore.`
			`// SPDX-License-Identifier: CC0-1.0`

			`module top(`
			`input wire [1:0] i,`
			`output wire [3:0] o`
			`);`
			`assign o = 4'd2 ** i;`
			`endmodule`