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28 lines
800 B
Plaintext
28 lines
800 B
Plaintext
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# See https://citation-file-format.github.io/
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cff-version: 1.2.0
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title: Verilator
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message: >-
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If you use this software, please cite it using the
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metadata from this file.
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type: software
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authors:
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- given-names: Wilson
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family-names: Snyder
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email: wsnyder@wsnyder.org
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affiliation: Veripool
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- given-names: Paul
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family-names: Wasson
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- given-names: Duane
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family-names: Galbi
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- name: 'et al'
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repository-code: 'https://github.com/verilator/verilator'
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url: 'https://verilator.org'
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abstract: >-
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The Verilator package converts Verilog and SystemVerilog hardware
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description language (HDL) designs into a fast C++ or SystemC model
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that, after compiling, can be executed. Verilator is not a
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traditional simulator but a compiler.
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license:
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- LGPL-3.0-only
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- Artistic-2.0
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