2022-04-29 15:32:02 +00:00
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%Warning-COMBDLY: t/t_lint_latch_bad_2.v:13:10: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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13 | o <= b;
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| ^~
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... For warning description see https://verilator.org/warn/COMBDLY?v=latest
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... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
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*** See https://verilator.org/warn/COMBDLY before disabling this,
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else you may end up with different sim results.
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2021-01-05 19:26:01 +00:00
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%Warning-LATCH: t/t_lint_latch_bad_2.v:11:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value)
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: ... Suggest use of always_latch for intentional latches
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11 | always @(a or b)
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| ^~~~~~
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%Error: Exiting due to
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