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64 lines
1.5 KiB
Systemverilog
64 lines
1.5 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// See also t_class_param.v
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module t (/*AUTOARG*/);
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class Cls #(parameter P = 12);
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bit [P-1:0] member;
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function bit [P-1:0] get_member;
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return member;
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endfunction
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function int get_p;
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return P;
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endfunction
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endclass
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class Wrap #(parameter PMINUS1 = 3);
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localparam P = PMINUS1 + 1;
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Cls#(P) c1;
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function int get_p;
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return c1.get_p();
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endfunction
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endclass
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typedef Cls#(5) Cls5_t;
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Cls c12;
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Cls #(.P(4)) c4;
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Cls5_t c5;
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Wrap #(.PMINUS1(15)) w16;
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initial begin
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c12 = new;
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c4 = new;
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c5 = new;
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w16 = new;
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if (c12.P != 12) $stop;
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if (c4.P != 4) $stop;
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if (c5.P != 5) $stop;
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if (c12.get_p() != 12) $stop;
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if (c4.get_p() != 4) $stop;
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if (c5.get_p() != 5) $stop;
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if (w16.get_p() != 16) $stop;
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// verilator lint_off WIDTH
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c12.member = 32'haaaaaaaa;
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c4.member = 32'haaaaaaaa;
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c5.member = 32'haaaaaaaa;
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// verilator lint_on WIDTH
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if (c12.member != 12'haaa) $stop;
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if (c4.member != 4'ha) $stop;
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if (c12.get_member() != 12'haaa) $stop;
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if (c4.get_member() != 4'ha) $stop;
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if ($sformatf("%p", c12) != "'{member:'haaa}") $stop;
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if ($sformatf("%p", c4) != "'{member:'ha}") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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