2021-04-11 22:55:06 +00:00
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.. Copyright 2003-2021 by Wilson Snyder.
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.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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*****
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Files
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*****
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.. _Files in the Distribution:
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Files in the Git Tree
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=====================
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The following is a summary of the files in the Git Tree (distribution) of
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Verilator:
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::
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Changes => Version history
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README.rst => This document
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bin/verilator => Compiler wrapper invoked to Verilate code
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docs/ => Additional documentation
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examples/ => Examples (see manual for descriptions)
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include/ => Files that should be in your -I compiler path
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include/verilated*.cpp => Global routines to link into your simulator
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include/verilated*.h => Global headers
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include/verilated.mk => Common Makefile
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src/ => Translator source code
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test_regress => Internal tests
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.. _Files Read/Written:
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Files Read/Written
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==================
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All output files are placed in the output directory specified with the
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:vlopt:`--Mdir` option, or "obj_dir" if not specified.
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Verilator creates the following files in the output directory:
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For --cc/--sc, it creates:
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.. list-table::
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* - *{prefix}*\ .cmake
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- CMake include script for compiling (from --make cmake)
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* - *{prefix}*\ .mk
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- Make include file for compiling (from --make gmake)
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* - *{prefix}*\ _classes.mk
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- Make include file with class names (from --make gmake)
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* - *{prefix}*\ _hier.mk
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- Make file for hierarchy blocks (from --make gmake)
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* - *{prefix|*\ _hierMkArgs.f
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- Arguments for hierarchical Verilation (from --make gmake)
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* - *{prefix}*\ _hierCMakeArgs.f
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- Arguments for hierarchical Verilation (from --make cmake)
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* - *{prefix}*\ .h
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
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- Model header
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* - *{prefix}*\ .cpp
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- Model C++ file
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* - *{prefix}*\ ___024root.h
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- Top level (SystemVerilog $root) internal header file
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* - *{prefix}*\ ___024root.cpp
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- Top level (SystemVerilog $root) internal C++ file
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* - *{prefix}*___024root*{__n}*\ .cpp
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- Additional top level internal C++ files (from --output-split)
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* - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
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2021-04-11 22:55:06 +00:00
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- Infrequent cold routines
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
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* - *{prefix}*\ ___024root__Trace{__n}*\ .cpp
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- Wave file generation code (from --trace)
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* - *{prefix}*\ ___024root__Trace__Slow{__n}*\ .cpp
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- Wave file generation code (from --trace)
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2021-04-11 22:55:06 +00:00
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* - *{prefix}*\ __Dpi.h
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- DPI import and export declarations (from --dpi)
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
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* - *{prefix}*\ __Dpi.cpp
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- Global DPI export wrappers (from --dpi)
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* - *{prefix}*\ __Dpi_Export\ *{__n}\ .cpp
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- DPI export wrappers scoped to this particular model (from --dpi)
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2021-04-11 22:55:06 +00:00
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* - *{prefix}*\ __Inlines.h
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- Inline support functions
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* - *{prefix}*\ __Syms.h
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- Global symbol table header
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
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* - *{prefix}*\ __Syms.cpp
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- Global symbol table C++
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2021-04-11 22:55:06 +00:00
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* - *{prefix}{each_verilog_module}*\ .h
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- Lower level internal header files
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
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* - *{prefix}{each_verilog_module}*\ .cpp
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- Lower level internal C++ files
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2021-04-11 22:55:06 +00:00
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* - *{prefix}{each_verilog_module}{__n}*\ .cpp
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- Additional lower C++ files (from --output-split)
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For --hierarchy mode, it creates:
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.. list-table::
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* - V\ *{hier_block}*\ /
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- Directory to Verilate each hierarchy block (from --hierarchy)
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* - *{prefix}*\ __hierVer.d
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- Make dependencies of the top module (from --hierarchy)
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* - *{prefix}*\ __hier.dir
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- Directory to store .dot, .vpp, .tree of top module (from --hierarchy)
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In certain debug and other modes, it also creates:
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.. list-table::
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* - *{prefix}*\ .xml
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- XML tree information (from --xml)
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* - *{prefix}*\ __cdc.txt
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- Clock Domain Crossing checks (from --cdc)
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* - *{prefix}*\ __stats.txt
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- Statistics (from --stats)
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* - *{prefix}*\ __idmap.txt
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- Symbol demangling (from --protect-ids)
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* - *{prefix}*\ __ver.d
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- Make dependencies (from -MMD)
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* - *{prefix}*\ __verFiles.dat
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- Timestamps (from --skip-identical)
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* - *{prefix}{misc}*\ .dot
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- Debugging graph files (from --debug)
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* - *{prefix}{misc}*\ .tree
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- Debugging files (from --debug)
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* - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp
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- Pre-processed verilog (from --debug)
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After running Make, the C++ compiler may produce the following:
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.. list-table::
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* - verilated{misc}*\ .d
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- Intermediate dependencies
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* - verilated{misc}*\ .o
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- Intermediate objects
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* - {mod_prefix}{misc}*\ .d
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- Intermediate dependencies
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* - {mod_prefix}{misc}*\ .o
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- Intermediate objects
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* - *{prefix}*\
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- Final executable (from --exe)
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* - *{prefix}*\ __ALL.a
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- Library of all Verilated objects
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* - *{prefix}*\ __ALL.cpp
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- Include of all code for single compile
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* - *{prefix}{misc}*\ .d
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- Intermediate dependencies
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* - *{prefix}{misc}*\ .o
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- Intermediate objects
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