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60 lines
1.4 KiB
Coq
60 lines
1.4 KiB
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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\escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9 ,
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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output \escaped_normal ;
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wire \escaped_normal = cyc[0];
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output double__underscore ;
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wire double__underscore = cyc[0];
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// C doesn't allow leading non-alpha, so must escape
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output \9num ;
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wire \9num = cyc[0];
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output \bra[ket]slash/dash-colon:9 ;
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wire \bra[ket]slash/dash-colon:9 = cyc[0];
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wire \check_alias = cyc[0];
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wire \check:alias = cyc[0];
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wire \check;alias = !cyc[0];
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`ifndef verilator
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initial begin
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$dumpfile("obj_dir/t_var_escape_dump.vcd");
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$dumpvars( 0, t );
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$dumpon;
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end
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`endif
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (escaped_normal != cyc[0]) $stop;
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if (\escaped_normal != cyc[0]) $stop;
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if (double__underscore != cyc[0]) $stop;
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if (\9num != cyc[0]) $stop;
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if (\bra[ket]slash/dash-colon:9 != cyc[0]) $stop;
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if (\check_alias != cyc[0]) $stop;
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if (\check:alias != cyc[0]) $stop;
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if (\check;alias != !cyc[0]) $stop;
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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