2013-02-14 00:03:10 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// No endian warning here
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2018-11-26 22:58:18 +00:00
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reg [7:0] pack [3:0];
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2013-02-14 00:03:10 +00:00
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initial begin
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pack[0] = 8'h78;
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pack[1] = 8'h88;
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pack[2] = 8'h98;
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pack[3] = 8'hA8;
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if (pack[0] !== 8'h78) $stop;
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if (pack[1] !== 8'h88) $stop;
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if (pack[2] !== 8'h98) $stop;
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if (pack[3] !== 8'hA8) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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