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32 lines
627 B
Systemverilog
32 lines
627 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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string qs[$];
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string as[];
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string s;
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initial begin
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s = {>>{qs}};
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if (s != "") $stop;
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s = {>>{as}};
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if (s != "") $stop;
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qs = '{"ab", "c", ""};
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s = {>>{qs}};
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if (s != "abc") $stop;
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as = new[3];
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as[0] = "abcd";
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as[2] = "ef";
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s = {>>{as}};
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if (s != "abcdef") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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