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34 lines
1.0 KiB
Systemverilog
34 lines
1.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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localparam int unsigned SPI_INDEX = 0;
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localparam int unsigned I2C_INDEX = 1;
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localparam int unsigned TMR_INDEX = 4;
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localparam logic [31:0] AHB_ADDR[6] = '{
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SPI_INDEX: 32'h80001000,
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I2C_INDEX: 32'h80002000,
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TMR_INDEX: 32'h80003000,
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default: '0};
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initial begin
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`checkh(AHB_ADDR[0], 32'h80001000);
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`checkh(AHB_ADDR[1], 32'h80002000);
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`checkh(AHB_ADDR[2], 32'h0);
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`checkh(AHB_ADDR[3], 32'h0);
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`checkh(AHB_ADDR[4], 32'h80003000);
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`checkh(AHB_ADDR[5], 32'h0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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