verilator/test_regress/t/t_order_clkinst.out

$version Generated by VerilatedVcd $end
$timescale 1ps $end

 $scope module top $end
  $var wire 1 # clk $end
  $scope module t $end
   $var wire 1 # clk $end
   $var wire 1 $ c1_start $end
   $var wire 32 % c1_count [31:0] $end
   $var wire 1 $ s2_start $end
   $var wire 32 & s2_count [31:0] $end
   $var wire 1 ' c3_start $end
   $var wire 32 ( c3_count [31:0] $end
   $var wire 8 ) cyc [7:0] $end
   $scope module c1 $end
    $var wire 1 $ start $end
    $var wire 32 % count [31:0] $end
    $var wire 32 * runnerm1 [31:0] $end
    $var wire 32 + runner [31:0] $end
   $upscope $end
   $scope module c3 $end
    $var wire 1 ' start $end
    $var wire 32 ( count [31:0] $end
    $var wire 32 , runnerm1 [31:0] $end
    $var wire 32 - runner [31:0] $end
   $upscope $end
   $scope module s2 $end
    $var wire 1 $ start $end
    $var wire 32 & count [31:0] $end
    $var wire 32 . runnerm1 [31:0] $end
    $var wire 32 / runner [31:0] $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0#
0$
b00000000000000000000000000000000 %
b00000000000000000000000000000000 &
0'
b00000000000000000000000000000000 (
b00000000 )
b11111111111111111111111111111111 *
b00000000000000000000000000000000 +
b11111111111111111111111111111111 ,
b00000000000000000000000000000000 -
b11111111111111111111111111111111 .
b00000000000000000000000000000000 /
#10
1#
b00000001 )
#15
0#
#20
1#
1$
b00000000000000000000000000000011 %
b00000000000000000000000000000011 &
1'
b00000000000000000000000000000011 (
b00000010 )
#25
0#
#30
1#
b00000011 )
#35
0#
#40
1#
b00000100 )