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21 lines
455 B
Systemverilog
21 lines
455 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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outl, outr,
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// Inputs
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lhs
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);
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input [95:0] lhs;
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output [95:0] outl;
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output [95:0] outr;
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assign outl = lhs << 95'hffff_00000000;
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assign outr = lhs >> 95'hffff_00000000;
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endmodule
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