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22 lines
507 B
Systemverilog
22 lines
507 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Alex Mykyta.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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logic clk = 0;
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logic x;
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logic y;
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always #1ns clk = ~clk;
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clocking cb @(posedge clk);
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output #1ns x;
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input #1step y;
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endclocking
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initial begin
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repeat(10) @(posedge clk);
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$display("*-* All Finished *-*");
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$finish();
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end
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endmodule
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