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22 lines
482 B
Systemverilog
22 lines
482 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module for Issue#xxxx
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Julien Margetts
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// SPDX-License-Identifier: Unlicense
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module test #(parameter W = 65)
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(input logic [W-1:0] a,
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input logic e,
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output logic [W-1:0] z);
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integer i;
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always @(*)
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if (e)
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for (i=0;i<W;i=i+1)
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z[i] = a[i];
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else
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z = W'(0);
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endmodule
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