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23 lines
496 B
Systemverilog
23 lines
496 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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int i;
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initial begin
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begin : named
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for (i = 0; i < 10; ++i) begin : loop
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if (i == 5) disable t.named;
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end
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end
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if (i != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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