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19 lines
425 B
Systemverilog
19 lines
425 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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typedef integer q_t[$];
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function void queue_set(ref q_t q);
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q.push_back(42);
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endfunction
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initial begin
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q_t iq;
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queue_set(42); // 42 is bad, meant iq
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end
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endmodule
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