2022-04-29 15:32:02 +00:00
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%Warning-COMBDLY: t/t_lint_nolatch_bad.v:13:10: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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13 | o <= b;
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| ^~
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... For warning description see https://verilator.org/warn/COMBDLY?v=latest
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... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
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*** See https://verilator.org/warn/COMBDLY before disabling this,
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else you may end up with different sim results.
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2021-01-05 19:26:01 +00:00
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%Warning-NOLATCH: t/t_lint_nolatch_bad.v:11:4: No latches detected in always_latch block
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11 | always_latch @(a or b)
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| ^~~~~~~~~~~~
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%Error: Exiting due to
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