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13 lines
399 B
Systemverilog
13 lines
399 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Ethan Sifferman.
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// SPDX-License-Identifier: CC0-1.0
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string MATCH_VERSION = "10.20";
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module t;
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logic usignal_contents_suppress; // Suppressed with -contents
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logic usignal_contents_mismatch; // Doesn't match -contents
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endmodule
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