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30 lines
690 B
Systemverilog
30 lines
690 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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function int fun(int val);
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fork
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$display("abc");
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$display("def");
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join_none // Although join is illegal, join_none legal (IEEE 1800-2023 13.4)
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return val + 2;
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endfunction
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task tsk();
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fork
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$display("ghi");
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$display("jkl");
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join_none
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endtask
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initial begin
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$display("$d", fun(2));
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tsk();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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