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31 lines
893 B
Systemverilog
31 lines
893 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/);
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wire [5:0] b1 = 6'b101101;
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wire [5:0] b2 = 6'b011110;
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logic [5:0] a6;
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logic [9:0] a10;
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initial begin
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// issue #3417
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a6 = b2 - b1;
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`checkh(a6, 6'h31);
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a10 = 10'(b2 - b1);
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`checkh(a10, 10'h3f1); // This being not 31 indicates operator expands
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`checkh($bits(10'(b1)), 10);
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`checkh($bits(10'(b2 - b1)), 10);
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`checkh($bits(b2 - b1), 6);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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