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25 lines
768 B
Python
25 lines
768 B
Python
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_hier_trace.v"
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test.compile(verilator_flags2=[
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'--trace', '-j 4', 't/t_hier_trace_sub/t_hier_trace.vlt', '--top-module t', '--hierarchical',
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'--fno-inline', '-F t/t_hier_trace_sub/top.F'
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])
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test.execute(all_run_flags=['-j 4'])
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test.vcd_identical(test.trace_filename, test.golden_filename)
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test.passes()
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