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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile(verilator_flags2=["--stats"])
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test.execute(expect_filename=test.golden_filename)
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test.file_grep(test.obj_dir + "/" + test.vm_prefix + "__stats.txt",
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r'Node count, DISPLAY \s+ 44 \s+ 27 \s+ 27 \s+ 6')
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test.passes()
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