2024-09-08 17:00:03 +00:00
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#!/usr/bin/env python3
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2006-08-26 11:35:28 +00:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2024-01-01 08:19:59 +00:00
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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2020-03-21 15:24:24 +00:00
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# can redistribute it and/or modify it under the terms of either the GNU
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2009-05-04 21:07:57 +00:00
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2020-03-21 15:24:24 +00:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2006-08-26 11:35:28 +00:00
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2024-09-08 17:00:03 +00:00
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import vltest_bootstrap
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2018-05-08 00:42:28 +00:00
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2024-09-08 17:00:03 +00:00
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test.scenarios('simulator')
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test.top_filename = "t/t_delay_incr.v"
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test.main_time_multiplier = 10e-7 / 10e-9
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2006-08-26 11:35:28 +00:00
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2024-09-08 17:00:03 +00:00
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test.compile(timing_loop=True, verilator_flags2=['--binary --timing -Wno-ZERODLY'])
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2006-08-26 11:35:28 +00:00
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2024-09-08 17:00:03 +00:00
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test.execute()
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test.passes()
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