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28 lines
608 B
Systemverilog
28 lines
608 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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static function bit get_first(bit q[$] = {1'b1});
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return q[0];
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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bit first;
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bit arg[$] = {1'b0, 1'b1};
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first = Foo::get_first();
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if (first != 1) $stop;
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first = Foo::get_first(arg);
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if (first != 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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