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55 lines
1.2 KiB
Systemverilog
55 lines
1.2 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum {TEN=10,
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ELEVEN=11,
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SIXTEEN=16} enum_t;
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int i;
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int cyc;
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enum_t en;
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// Test loop
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always @ (posedge clk) begin
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i = $cast(en, cyc);
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d i=%0d en=%0d\n",$time, cyc, i, en);
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`endif
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cyc <= cyc + 1;
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if (cyc == 10) begin
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if (i != 1) $stop;
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if (en != TEN) $stop;
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end
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else if (cyc == 11) begin
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if (i != 1) $stop;
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if (en != ELEVEN) $stop;
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end
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else if (cyc == 12) begin
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if (i != 0) $stop;
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if (en != ELEVEN) $stop;
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end
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else if (cyc == 16) begin
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if (i != 1) $stop;
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if (en != SIXTEEN) $stop;
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end
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else if (cyc == 17) begin
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if (i != 0) $stop;
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if (en != SIXTEEN) $stop;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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