verilator/docs/gen/ex_DIDNOTCONVERGE_msg.rst

.. comment: generated by t_lint_didnotconverge_bad
.. code-block::

   -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] a)
   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
Commentary 2021-09-18 00:03:45 +00:00			`.. comment: generated by t_lint_didnotconverge_bad`
			`.. code-block::`

DFG: handle simple always blocks 2022-10-01 11:28:16 +00:00			`-V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] a)`
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`%Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.`