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25 lines
489 B
Systemverilog
25 lines
489 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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static task do_something();
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`ifdef USE_STD_PREFIX
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std::process p;
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`else
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process p;
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`endif
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p = process::self();
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endtask
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endclass
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module t();
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initial begin
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Foo::do_something();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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