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32 lines
525 B
Systemverilog
32 lines
525 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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localparam PARAM = 10;
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endpackage
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package pkg;
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localparam PARAM = 10;
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endpackage
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module sub import pkg::*;
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#( ) ();
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endmodule
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package pkg;
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endpackage
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package pkg;
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endpackage
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module t (/*AUTOARG*/);
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sub sub ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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