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13 lines
334 B
Systemverilog
13 lines
334 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module v(input logic t);
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endmodule
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module top(input logic [2:0] c);
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v v1((int'(c) + int'($countones(c))) > 2);
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endmodule
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