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20 lines
383 B
Systemverilog
20 lines
383 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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int member;
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task method; endtask
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endclass
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module t;
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initial begin
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Foo foo = new;
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Foo::member = 1;
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Foo::method();
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end
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endmodule
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