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35 lines
595 B
Systemverilog
35 lines
595 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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program;
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task atask;
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endtask
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function int afunc(input int i);
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return i+1;
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endfunction
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class acls;
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static int i = 10;
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endclass
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endprogram
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program t(/*AUTOARG*/);
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int i;
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initial begin
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atask();
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i = afunc(2);
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if (i != 3) $stop;
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if (acls::i != 10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endprogram
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