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78 lines
1.9 KiB
Systemverilog
78 lines
1.9 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t(/*AUTOARG*/);
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integer seed;
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integer r;
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integer sum;
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initial begin
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// Illegal values
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seed = 1234;
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r = $dist_chi_square(seed, 5);
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`checkd(seed, 923940542);
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`checkd(r, 8);
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sum = 1;
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repeat(20) sum += $dist_chi_square(seed, 5);
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`checkd(sum, 130);
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seed = 1234;
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r = $dist_erlang(seed, 5, 10);
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`checkd(seed, 1025211431);
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`checkd(r, 19);
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sum = 1;
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repeat(20) sum += $dist_erlang(seed, 5, 10);
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`checkd(sum, 173);
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seed = 1234;
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r = $dist_exponential(seed, 5);
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`checkd(seed, 85231147);
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`checkd(r, 20);
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sum = 1;
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repeat(20) sum += $dist_exponential(seed, 5);
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`checkd(sum, 104);
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seed = 1234;
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r = $dist_normal(seed, 5, 10);
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`checkd(seed, -1570070672);
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`checkd(r, 4);
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sum = 1;
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repeat(20) sum += $dist_normal(seed, 5, 10);
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`checkd(sum, 114);
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seed = 1234;
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r = $dist_poisson(seed, 5);
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`checkd(seed, 418012337);
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`checkd(r, 2);
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sum = 1;
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repeat(20) sum += $dist_poisson(seed, 5);
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`checkd(sum, 111);
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seed = 1234;
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r = $dist_t(seed, 5);
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`checkd(seed, -797481412);
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`checkd(r, 0);
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sum = 1;
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repeat(20) sum += $dist_t(seed, 5);
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`checkd(sum, -2);
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seed = 1234;
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r = $dist_uniform(seed, 5, 10);
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`checkd(seed, 85231147);
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`checkd(r, 5);
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sum = 1;
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repeat(20) sum += $dist_uniform(seed, 5, 10);
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`checkd(sum, 147);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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