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36 lines
648 B
Systemverilog
36 lines
648 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface class Icempty;
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endclass : Icempty
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package Pkg;
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class Icls1 #(parameter PARAM = 12);
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localparam LP1 = 1;
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function int getParam();
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return PARAM;
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endfunction
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endclass
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endpackage
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class Cls12 extends Pkg::Icls1;
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endclass
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module t(/*AUTOARG*/);
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Cls12 cp12;
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initial begin
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cp12 = new;
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if (cp12.getParam() != 12) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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