verilator/test_regress/t/t_lint_latch_bad_2.out

%Warning-LATCH: t/t_lint_latch_bad_2.v:11:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value)
                                           : ... Suggest use of always_latch for intentional latches
   11 |    always_comb
      |    ^~~~~~~~~~~
                ... For warning description see https://verilator.org/warn/LATCH?v=latest
                ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.
%Error: Exiting due to
Add LATCH and NOLATCH warnings (#1609) (#2740). 2021-01-05 19:26:01 +00:00			`%Warning-LATCH: t/t_lint_latch_bad_2.v:11:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value)`
			`: ... Suggest use of always_latch for intentional latches`
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`11 \| always_comb`
			`\| ^~~~~~~~~~~`
			`... For warning description see https://verilator.org/warn/LATCH?v=latest`
			`... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.`
Add LATCH and NOLATCH warnings (#1609) (#2740). 2021-01-05 19:26:01 +00:00			`%Error: Exiting due to`