2020-05-25 20:12:34 +00:00
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt_all => 1);
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top_filename("t/t_flag_csplit.v");
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while (1) {
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2023-01-08 23:17:24 +00:00
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# This rule requires GNU make > 4.1 (or so, known broken in 3.81)
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2020-05-25 20:12:34 +00:00
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#%__Slow.o: %__Slow.cpp
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# $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_SLOW) -c -o $@ $<
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if (make_version() < 4.1) {
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skip("Test requires GNU Make version >= 4.1");
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last;
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}
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compile(
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v_flags2 => ["--trace --output-split 0 --exe ../$Self->{main_filename}"],
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verilator_make_gmake => 0,
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);
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# We don't use the standard test_regress rules, as want to test the rules
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# properly build
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run(logfile => "$Self->{obj_dir}/vlt_gcc.log",
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tee => $self->{verbose},
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2020-05-31 13:03:51 +00:00
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cmd=>[$ENV{MAKE},
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2021-09-08 22:45:25 +00:00
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"-C " . $Self->{obj_dir},
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2020-05-25 20:12:34 +00:00
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"-f $Self->{VM_PREFIX}.mk",
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"-j 4",
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"VM_PREFIX=$Self->{VM_PREFIX}",
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"TEST_OBJ_DIR=$Self->{obj_dir}",
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"CPPFLAGS_DRIVER=-D".uc($Self->{name}),
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2021-09-08 22:45:25 +00:00
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($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1" : ""),
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2020-05-25 20:12:34 +00:00
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"OPT_FAST=-O2",
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"OPT_SLOW=-O0",
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($param{make_flags}||""),
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]);
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execute(
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check_finished => 1,
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);
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# Never spliting, so should set VM_PARALLEL_BUILDS to 0 by default
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file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}_classes.mk", qr/VM_PARALLEL_BUILDS\s*=\s*0/);
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check_no_splits();
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check_all_file();
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check_gcc_flags("$Self->{obj_dir}/vlt_gcc.log");
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ok(1);
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last;
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}
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1;
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sub check_no_splits {
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foreach my $file (glob("$Self->{obj_dir}/*.cpp")) {
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Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.
Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
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$file =~ s/__024root//;
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2021-07-14 21:37:37 +00:00
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if ($file =~ qr/__[1-9]/) {
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2020-05-25 20:12:34 +00:00
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error("Split file found: $file");
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}
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}
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}
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sub check_all_file {
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foreach my $file (glob("$Self->{obj_dir}/*.cpp")) {
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if ($file =~ qr/__ALL.cpp/) {
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return;
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}
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}
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error("__ALL.cpp file not found");
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}
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sub check_gcc_flags {
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my $filename = shift;
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my $fh = IO::File->new("<$filename") or error("$! $filenme");
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2021-09-08 22:45:25 +00:00
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while (defined(my $line = $fh->getline)) {
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2020-05-25 20:12:34 +00:00
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chomp $line;
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print ":log: $line\n" if $Self->{verbose};
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if ($line =~ /\.cpp/ && $line =~ qr/-O0/) {
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error("File built as slow (should be in __ALL.cpp) : $line");
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}
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}
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}
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