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102 lines
2.0 KiB
Systemverilog
102 lines
2.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Foo;
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int x;
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function new;
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this.x = 10;
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endfunction
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endclass
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class Bar extends Foo;
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function new;
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super.new;
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endfunction
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endclass
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class BarUnusedArg extends Foo;
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function new (int a);
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super.new;
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endfunction
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endclass
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class FooArg;
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int x;
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function new (int a);
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this.x = a;
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endfunction
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endclass
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class BarArg extends FooArg;
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function new (int a);
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super.new(a);
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endfunction
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endclass
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class BarExpr extends FooArg;
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function new (int a, string b);
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super.new(a + b.len());
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endfunction
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endclass
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class Foo2Args;
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int x;
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function new (int a, int b);
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this.x = a + b;
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endfunction
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endclass
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class Bar2Args extends Foo2Args;
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function new (int a, int b);
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super.new(a, b);
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endfunction
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endclass
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module t (/*AUTOARG*/
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);
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class FooInModule;
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int x;
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function new;
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this.x = 15;
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endfunction
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endclass
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class BarInModule extends FooInModule;
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function new;
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super.new;
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endfunction
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endclass
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Bar bar;
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BarInModule barInModule;
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BarUnusedArg barUnusedArg;
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BarArg barArg;
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BarExpr barExpr;
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Bar2Args bar2Args;
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initial begin
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bar = new;
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`checkh(bar.x, 10);
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barInModule = new;
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`checkh(barInModule.x, 15);
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barUnusedArg = new(2);
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`checkh(barUnusedArg.x, 10);
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barArg = new(2);
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`checkh(barArg.x, 2);
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barExpr = new (7, "ABCDEFGHI");
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`checkh(barExpr.x, 16);
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bar2Args = new(2, 12);
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`checkh(bar2Args.x, 14);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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