mirror of
https://github.com/verilator/verilator.git
synced 2025-01-08 15:47:36 +00:00
18 lines
281 B
Coq
18 lines
281 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
//
|
||
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
// without warranty, 2017 by Wilson Snyder.
|
||
|
|
||
|
module t (/*AUTOARG*/
|
||
|
// Inputs
|
||
|
clk
|
||
|
);
|
||
|
|
||
|
input clk;
|
||
|
|
||
|
always_comb @(*) begin
|
||
|
$stop;
|
||
|
end
|
||
|
|
||
|
endmodule
|