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24 lines
666 B
Systemverilog
24 lines
666 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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function automatic real logWrapper(real x);
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return $ln(x);
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endfunction
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initial begin
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// See bug4543
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$display("bad x=%f, y=%f", logWrapper(10.0), 1.0 * logWrapper(10.0));
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$display("noc x=%f, y=%f", $ln(10.0), 1.0 * $ln(10.0));
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if (logWrapper(10.0) != $ln(10.0)) $stop;
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if (logWrapper(10.0) != 1.0 * logWrapper(10.0)) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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