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20 lines
401 B
Systemverilog
20 lines
401 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int m_one;
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constraint cons { m_one > 0 && m_one < 2; }
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task test1;
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cons.bad_method(1); // BAD
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endtask
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endclass
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module t (/*AUTOARG*/);
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endmodule
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