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23 lines
701 B
Systemverilog
23 lines
701 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls #(parameter PARAMB = 12);
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endclass
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class Cls2 #(parameter PARAMB = 13, parameter PARAMC = 14);
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endclass
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module t (/*AUTOARG*/);
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Cls #(.PARAMBAD(1)) c; // Bad param name
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Cls #(13, 1) cd; // Bad param number
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Cls #(.PARAMB(14),) ce; // Bad superfluous comma
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Cls #(14,) cf; // Bad superfluous comma
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Cls2 #(15,) cg; // Bad superfluous comma
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Cls2 #(.PARAMB(16),) ch; // Bad superfluous comma
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Cls2 #(.PARAMC(17),) ci; // Bad superfluous comma
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endmodule
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